FIG. 5 is a diagram showing an example of a typical configuration of a clock and data recovery circuit that extracts from received data a clock signal synchronized with the received data and outputs the extracted clock signal and data. Referring to FIG. 5, a four-phase clock generation circuit (abbreviated as a “four-phase generation circuit”) 10 receives a clock signal CLK generated by a PLL (Phase Locked Loop) circuit or the like not shown, and generates four-phase clock signals with phases thereof mutually spaced by 90 degrees by frequency division of the clock signal CLK.
A first selector 201 receives the clock signals with phases of 0 and 180 degrees output from the four-phase generation circuit 10, selects one of the clock signals with the phases of 0 and 180 degrees, based on a 0 or 180 selection signal, and outputs the selected signal. A second selector 202 receives the clock signals with phases of 90 and 270 degrees output from the four-phase generation circuit 10, selects one of the clock signals with the phases of 90 and 270 degrees, based on a 90 or 270 selection signal, and outputs the selected signal. A third selector 203 receives the clock signals with the phases of 0 and 180 degrees output from the four-phase generation circuit 10, selects one of the clock signals with the phases of 0 and 180 degrees, based on the 0 or 180 selection signal, and outputs the selected signal. A fourth selector 204 receives the clock signals with the phases of 90 and 270 degrees output from the four-phase generation circuit 10, selects one of the clock signals with the phases of 90 and 270 degrees, based on the 90 or 270 selection signal, and outputs the selected signal
A first interpolator 301 receives the outputs of the first selector 201 and the second selector 202 and outputs signals with phases obtained by interpolation of a phase difference between the input two signals according to an interpolator control signal from a control circuit 70′, as a 0 data latch clock signal and a 180 data latch clock signal (differential clock signals).
A second interpolator 302 receives the outputs of the third selector 203 and the fourth selector 204 and outputs signals with phases obtained by interpolation of a phase difference between the input two signals according to the interpolator control signal from the control circuit 70′, as a 90 edge clock signal and a 270 edge clock signal (differential clock signals).
A receiver 40 receives serial data and outputs the received serial data.
A first latch 501 samples the received serial data at a rising edge of the 0 data latch clock signal from the first interpolator 301, and outputs the sampled data (even data).
A second latch 502 samples the received serial data at a rising edge of the 180 data latch clock signal (clock signal with a phase reverse to the phase of the 0 edge latch clock signal) from the first interpolator 301, and outputs the sampled data (odd data).
A third latch 503 samples the received serial data at a rising edge of the 90 edge latch signal from the second interpolator 302.
A fourth latch 504 samples the received serial data at a rising edge of the 270 edge latch clock signal (clock signal with a phase reverse to the phase of the 90 edge latch clock signal) from the second interpolator 302.
To a digital filter 60′, outputs of first through fourth latches 501 through 504 are supplied, and the digital filter 60′ outputs an UP signal which is a control signal for advancing the phases or a DOWN signal which is a control signal for delaying the phases, based on a result of filter processing.
Based on the UP or DOWN signal, the control circuit 70′ outputs the 0 or 180 selection signal, 90 or 270 selection signal, and interpolator control signal. The 0 or 180 selection signal and the 90 or 270 selection signal cause the second selector 202 and the fourth selector 204 to select 90 degrees from the four-phase generation circuit 10 when the first selector 201 and the third selector 203 selects 0 degrees from the four-phase selection circuit 10. When the first selector 201 and the third selector 203 selects 180 degrees from the four-phase generation circuit 10, the 0 or 180 selection signal and the 90 or 270 selection signal cause the second selector 202 and the fourth selector 204 to select 270 degrees. In other words, assume that in accordance with the UP or DOWN signal, an internal division value (a value x used in internal division of x: 1−x) of the phase difference at each of the interpolators 301 and 302 becomes larger than one or smaller than zero (overflow or underflow) in the control circuit 70′ when the first selector 201 and the third selector 203 select the clock signal with a certain phase from the four-phase generation circuit 10 and the second selector 202 and the fourth selector 204 select the clock signal with a certain phase from the four-phase generation circuit 10. Then, the 0 or 180 control signal and the 90 or 270 control signal cause the first selector 201 and the third selector 203 and the second selector 202 and the fourth selector 204 to perform switching to the clock signals with other phases from the fourth-phase generation circuit 10, respectively.
FIG. 6 is a timing waveform diagram explaining an operation of the circuit in FIG. 5. FIG. 6 illustrates eye patterns. A void portion of each of the even (even) data and the odd (odd) data indicates an eye opening. The serial data in which the even data and the odd data have been multiplexed at a transmission side is supplied to the receiver 40. The even (even) data is sampled by the latch 501 at the rising edge of the clock signal with the phase of zero degrees. The odd (odd) data is sampled by the latch 502 at the rising edge of the clock signal with the phase of 180 degrees (clock signal with the phase reverse to the phase of 0 degrees). Edges of the even data and the odd data are sampled at the rising edges of the clock signals with the phases of 90 and 270 degrees, respectively.
As a clock and data recovery circuit that includes interpolators, a description in Patent Document 1 may be referred to. Each interpolator may be constituted from a differential circuit as shown in FIG. 7, for example (refer to Patent Document 1), in addition to a CMOS circuit (such as those shown in FIGS. 4 and 6 of Patent Document 1). Referring to FIG. 7, this interpolator has a common load circuit. By changing currents that respectively flow through current sources CS1 and CS2 connected to a common source of a first differential pair (MN61, MN62) and a common source of a second differential pair (MN63, MN64), respectively, by a control signal ict1 [15:0], phases of differential output signals OUT and OUTB are variably controlled. The first differential pair receives first differential inputs IN1 and IN1B at gates thereof, respectively. The second differential pair receives second differential inputs IN2 and IN2B at gates thereof, respectively.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2002-190724A (FIGS. 4, 6, and 15)